The present invention relates in general to semiconductors and, more particularly, to a semiconductor packaging method.
Chip scale integrated circuits are small footprint devices in which a semiconductor die is mounted on a distribution substrate whose dimensions are approximately the same as the dimensions of the semiconductor die. The distribution substrate includes a set of attachment points for coupling to bonding pads of the semiconductor die, and a set of terminals for making external connections. Pads are coupled to the terminals using conductors routed along a surface of the distribution substrate.
In many cases, more than one hundred conductors are needed to interconnect the bonding pads and terminals. Routing these conductors with prior art methods is both time consuming and inefficient. For example, one prior art technique uses manual trial and error methods to route the conductors from the attachment points to the terminals, which can require several days to complete. Another prior art method uses an automatic routing program, which uses several hours of computer time to interconnect the distribution substrate. However, the prior art automatic routers constrain the attachment points to being placed on exact grid points or else limit the conductors to orthogonal angles. Such limitations increase the size of the integrated circuit packages along with the manufacturing cost.
Hence, there is a need for a more efficient method of interconnecting a distribution substrate which results in a smaller package and lower manufacturing cost.